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x28c010 1 5 volt, byte alterable e 2 prom ? xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3858-3.1 4/3/97 t1/c0/d0 sh features ? access time: 120ns ? simple byte and page write single 5v supply no external high voltages or v pp control circuits self-timed no erase before write no complex programming algorithms no overerase problem ? low power cmos: active: 50ma standby: 500 m a ? software data protection protects data against system level inadvertant writes ? high speed page write capability ? highly reliable direct write? cell endurance: 100,000 write cycles data retention: 100 years ? early end of write detection data polling toggle bit polling description the xicor x28c010 is a 128k x 8 e 2 prom, fabricated with xicor's proprietary, high performance, floating gate cmos technology. like all xicor programmable non- volatile memories the x28c010 is a 5v only device. the x28c010 features the jedec approved pinout for byte- wide memories, compatible with industry standard eproms. the x28c010 supports a 256-byte page write operation, effectively providing a 19 m s/byte write cycle and en- abling the entire memory to be typically written in less than 2.5 seconds. the x28c010 also features data polling and toggle bit polling, system software support schemes used to indicate the early completion of a write cycle. in addition, the x28c010 supports software data protection option. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. data retention is specified to be greater than 100 years. 1m x28c010 128k x 8 bit pin configurations 3858 fhd f02.1 nc a 16 a 15 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we nc a 14 a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 x28c010 cerdip flat pack soic (r) x28c010 (top view) a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 13 a 8 a 9 a 11 a 10 i/o 7 a 14 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 a 12 a 15 a 16 nc v cc we nc 232 6 1 5 43 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 oe ce a 7 14 21 30 x28c010 (top view) a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 a 13 a 8 a 9 a 11 a 10 i/o 7 a 14 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 i/o 6 a 12 a 15 a 16 nc v cc we nc 232 6 1 5 43 8 7 9 10 11 12 13 15 17 16 18 19 20 22 23 24 25 26 27 28 29 31 oe ce a 7 14 21 30 3858 fhd f03.1 plcc lcc extended lcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x28c010 3858 ill f21 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 nc nc v ss nc nc i/o 2 i/o 1 i/o 0 a 0 a 1 a 2 a 3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a 11 a 9 a 8 a 13 a 14 nc nc nc we v cc nc nc nc a 16 a 15 a 12 a 7 a 6 a 5 a 4 tsop x28c010 (bottom view) 14 a 0 16 i/o 1 18 v ss 11 a 3 9 a 5 7 a 7 15 i/o 0 17 i/o 2 19 i/o 3 5 a 15 2 nc 36 v cc 20 i/o 4 21 i/o 5 34 nc 23 i/o 7 25 a 10 27 a 11 29 a 8 22 i/o 6 32 nc 24 ce 26 oe 28 a 9 30 a 13 13 a 1 12 a 2 10 a 4 8 a 6 4 a 16 3 nc 1 nc 35 we 33 nc 31 a 14 6 a 12 pga 3858 fhd f20
2 x28c010 pin descriptions addresses (a 0 Ca 16 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable ( ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable ( oe ) the output enable input controls the data output buffers and is used to initiate read operations. data in/data out (i/o 0 Ci/o 7 ) data is written to or read from the x28c010 through the i/o pins. write enable ( we ) the write enable input controls the writing of data to the x28c010. pin names symbol description a 0 Ca 16 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect 3858 pgm t01 3858 fhd f01 functional diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 1m-bit e 2 prom array i/o 0 Ci/o 7 data inputs/outputs ce oe v cc v ss a 8 Ca 16 we a 0 Ca 7
x28c010 3 device operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe returning high. this two line control architecture elimi- nates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. write write operations are initiated when both ce and we are low and oe is high. the x28c010 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , which- ever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs first. a byte write operation, once initiated, will automatically continue to completion, typically within 5ms. page write operation the page write feature of the x28c010 allows the entire memory to be written in 5 seconds. page write allows two to two hundred fifty-six bytes of data to be consecu- tively written to the x28c010 prior to the commence- ment of the internal programming cycle. the host can fetch data from another device within the system during a page write operation (change the source address), but the page address (a 8 through a 16 ) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page write mode can be initiated during any write operation. following the initial byte write cycle, the host can write an additional one to two hundred fifty six bytes in the same manner as the first byte was written. each successive byte load cycle, started by the we high to low transition, must begin within 100 m s of the falling edge of the preceding we . if a subsequent we high to low transition is not detected within 100 m s, the internal automatic programming cycle will commence. there is no page write window limitation. effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100 m s. write operation status bits the x28c010 provides the user two write operation status bits. these can be used to optimize a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. data polling (i/o 7 ) the x28c010 features data polling as a method to indicate to the host system that the byte write or page write cycle has completed. data polling allows a simple bit test operation to determine the status of the x28c010, eliminating additional interrupt inputs or external hard- ware. during the internal programming cycle, any at- tempt to read the last byte written will produce the complement of that data on i/o 7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete, i/o 7 will reflect true data. note: if the x28c010 is in the protected state and an illegal write operation is attempted data polling will not operate. toggle bit (i/o 6 ) the x28c010 also provides another method for deter- mining when the internal write cycle is complete. during the internal programming cycle, i/o 6 will toggle from high to low and low to high on subsequent at- tempts to read the device. when the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. figure 1. status bit assignment 5 tb dp 43210 i/o reserved toggle bit data polling 3858 fhd f11
4 x28c010 data polling i/o 7 figure 2. data polling bus sequence figure 3. data polling software flow 3858 fhd f12 data polling can effectively halve the time for writing to the x28c010. the timing diagram in figure 2 illustrates the sequence of events on the bus. the software flow diagram in figure 3 illustrates one method of implement- ing the routine. 3858 fhd f13 write data save last data and address read last address i/o 7 compare? x28c010 ready no yes writes complete? no yes ce oe we i/o 7 x28c010 ready last write high z v ol v ih a 0 Ca 14 an an an an an an v oh an
x28c010 5 the toggle bit i/o 6 figure 4. toggle bit bus sequence figure 5. toggle bit software flow 3858 fhd f14 the toggle bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement data polling. this can be especially helpful in an array comprised of multiple x28c010 memories that is frequently updated. toggle bit polling can also provide a method for status checking in multiprocessor applications. the timing diagram in figure 4 illustrates the sequence of events on the bus. the software flow diagram in figure 5 illustrates a method for polling the toggle bit. 3858 fhd f15 ce oe we i/o 6 x28c010 ready v oh v ol last write high z * beginning and ending state of i/o 6 will vary. * * load accum from addr n compare accum with addr n x28c010 ready compare ok? no yes last write
6 x28c010 hardware data protection the x28c010 provides three hardware features that protect nonvolatile data from inadvertent writes. ? noise protectiona we pulse less than 10ns will not initiate a write cycle. ? default v cc senseall functions are inhibited when v cc is 3.5v. ? write inhibitholding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. software data protection the x28c010 offers a software controlled data protec- tion feature. the x28c010 is shipped from xicor with the software data protection not enabled: that is the device will be in the standard operating mode. in this mode data should be protected during power-up/-down operations through the use of external circuits. the host would then have open read and write access of the device once v cc was stable. the x28c010 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection fea- ture. the internal software data protection circuit is enabled after the first write operation utilizing the soft- ware algorithm. this circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the x28c010 is also protected from inadvertent and accidental writes in the powered-up state. that is, the software algorithm must be issued prior to writing additional data to the device. software algorithm selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific ad- dresses. refer to figures 6 and 7 for the sequence. the three byte sequence opens the page write window enabling the host to write from one to two hundred fifty- six bytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state.
x28c010 7 software data protection figure 6. timing sequencebyte or page write figure 7. write sequence for software data protection regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the x28c010 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the x28c010 will be write protected during power-down and after any subsequent power-up. the state of a 15 and a 16 while executing the algorithm is dont care. note: once initiated, the sequence of write operations should not be interrupted. 3858 fhd f16 3858 fhd f17 ce we (v cc ) write protected v cc 0v data addr aa 5555 55 2aaa a0 5555 t blc max writes ok byte or page t wc write last byte to last address write data 55 to address 2aaa write data a0 to address 5555 write data xx to any address after t wc re-enters data protected state write data aa to address 5555 optional byte/page load operation
8 x28c010 resetting software data protection figure 8. reset software data protection timing sequence ce we standard operating mode v cc data addr aa 5555 55 2aaa 80 5555 3 t wc aa 5555 55 2aaa 20 5555 3858 fhd f18 figure 9. software sequence to deactivate software data protection in the event the user wants to deactivate the software data protection feature for testing or reprogramming in an e 2 prom programmer, the following six step algo- rithm will reset the internal protection circuit. after t wc , the x28c010 will be in standard operating mode. note: once initiated, the sequence of write operations should not be interrupted. 3858 fhd f19 write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555
x28c010 9 system considerations because the x28c010 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. proper usage can provide the lowest possible power dissipation and elimi- nate the possibility of contention where multiple i/o pins share the same bus. to gain the most benefit it is recommended that ce be decoded from the address bus and be used as the primary device selection input. both oe and we would then be common among all devices in the array. for a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. because the x28c010 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. enabling ce will cause transient current spikes. the magnitude of these spikes is dependent on the output capacitive loading of the i/os. therefore, the larger the array sharing a common bus, the larger the transient spikes. the voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recommended that a 0.1 m f high fre- quency ceramic capacitor be used between v cc and v ss at each device. depending on the size of the array, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7 m f electrolytic bulk capacitor be placed between v cc and v ss for each eight devices employed in the array. this bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the pc board traces. active supply current vs. ambient temperature i cc (rd) by temperature over frequency standby supply current vs. ambient temperature ?5 ?0 +125 0.15 0.2 0.25 0.3 ambient temperature ( c) i sb (ma) 3858 ill f25 0.05 +35 +80 v cc = 5v 0.1 ?5 ?0 +125 12 14 16 18 ambient temperature ( c) i cc wr (ma) 3858 ill f24 10 +35 +80 v cc = 5v 0 315 30 40 50 5.0 v cc frequency (mhz) i cc rd (ma) 3858 ill f26 10 69 ?5 c +25 c +125 c 12 20 60
10 x28c010 *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. absolute maximum ratings* temperature under bias x28c010 ...................................... C10 c to +85 c x28c010i ................................... C65 c to +135 c x28c010m ................................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c recommend operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 3858 pgm t02 supply voltage limits x28c010 5v 10% 3858 pgm t03 d.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc v cc current (active) 50 ma ce = oe = v il , we = v ih , (ttl inputs) all i/os = open, address inputs = .4v/2.4v levels @ f = 5mhz i sb1 v cc current (standby) 3 ma ce = v ih , oe = v il (ttl inputs) all i/os = open, other inputs = v ih i sb2 v cc current (standby) 500 m a ce = v cc C 0.3v, oe = v il (cmos inputs) all i/os = open, other inputs = v cc i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc , ce = v ih v ll (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage 2.4 v i oh = C400 m a 3858 pgm t04.2 notes: (1) v il min. and v ih max. are for reference only and are not tested.
x28c010 11 endurance and data retention parameter min. max. units endurance 10,000 cycles per byte endurance 100,000 cycles per page data retention 100 years 3858 pgm t07.1 power-up timing symbol parameter max. units t pur (2) power-up to read operation 100 m s t puw (2) power-up to write operation 5 ms 3858 pgm t05 capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 10 pf v in = 0v 3858 pgm t06 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 3858 pgm t05.1 mode selection ce oe we mode i/o power l l h read d out active l h l write d in active h x x standby and high z standby write inhibit x l x write inhibit x x h write inhibit 3858 pgm t08 equivalent a.c. load circuit note: (2) this parameter is periodically sampled and not 100% tested. waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance symbol table 3858 fhd f04.3 5v 1.92k w 100pf output 1.37k w
12 x28c010 a.c. characteristics (over the recommended operating conditions, unless otherwise specified.) read cycle limits x28c010-12 x28c010-15 x28c010-20 x28c010-25 symbol parameter min. max. min. max. min. max. min. max. units t rc read cycle time 120 150 200 250 ns t ce chip enable access time 120 150 200 250 ns t aa address access time 120 150 200 250 ns t oe output enable access time 50 50 50 50 ns t lz (3) ce low to active output 0 0 0 0 ns t olz (3) oe low to active output 0 0 0 0 ns t hz (3) ce high to high z output 50 50 50 50 ns t ohz (3) oe high to high z output 50 50 50 50 ns t oh output hold from 0 0 0 0 ns address change 3858 pgm t09.1 read cycle note: (3) t lz min.,t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. 3858 fhd f05 t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z 3858 fhd f05
x28c010 13 write cycle limits symbol parameter min. max. units t wc (4) write cycle time 10 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 100 ns t oes oe high setup time 10 ns t oeh oe high hold time 10 ns t wp we pulse width 100 ns t wph we high recovery 100 ns t dv data valid 1 m s t ds data setup 50 ns t dh data hold 0 ns t dw delay to next write 10 m s t blc byte load cycle 0.2 100 m s 3858 pgm t10.1 we controlled write cycle notes: (4) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to complete internal write operation. 3858 fhd f06 address t as t wc t ah t oes t dv t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp t wph 3858 fhd f06
14 x28c010 ce controlled write cycle page write cycle notes: (5) between successive byte writes within a page write operation, oe can be strobed low: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively performing a polling operation. (6) the timings shown above are unique to page write operations. individual byte load operations within the page write must conform to either the ce or we controlled write cycle timing. 3858 fhd f07 address t as t oeh t wc t ah t oes t wph t cs t dv t ds t dh t ch ce we oe data in data out high z t cw data valid 3858 fhd f07 3858 fhd f08 we oe (5) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address * (6) i/o *for each successive write within the page write operation, a 8 Ca 16 should be the same or writes to an unknown address could occur.
x28c010 15 data polling timing diagram (7) 3858 fhd f09 toggle bit timing diagram ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary. 3858 fhd f10 note: (7) polling operations are by definition read cycles and are therefore subject to read cycle timings. address a n 3858 fhd f09 d in =x d out =x d out =x t wc t oeh t oes a n a n ce we oe i/o 7 t dw
16 x28c010 notes
x28c010 17 packaging information 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.018 (0.46) 1.690 (42.95) max. 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.232 (5.90) max. 0.060 (1.52) 0.015 (0.38) 3926 fhd f09 pin 1 seating plane 0.200 (5.08) 0.150 (3.18) 0.065 (1.65) 0.033 (0.84) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) max. 0 15 32-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 0.005 (0.13) min. 0.150 (3.8) min. 0.015 (0.33) 0.008 (0.20)
18 x28c010 packaging information 0.150 (3.81) bsc 0.300 (7.62) bsc 0.458 (11.63) CC 0.458 (11.63) 0.442 (11.22) pin 1 0.400 (10.16) bsc 0.560 (14.22) 0.540 (13.71) 3926 fhd f14 0.020 (0.51) x 45 ref. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) typ. (4) plcs. 0.040 (1.02) x 45 ref. typ. (3) plcs. 0.050 (1.27) bsc 0.028 (0.71) 0.022 (0.56) (32) plcs. 0.200 (5.08) bsc 0.558 (14.17) CC 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) pin 1 index corder 32-pad ceramic leadless chip carrier package type e note: 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: 1% nlt 0.005 (0.127)
x28c010 19 packaging information 3926 fhd f20 32-lead ceramic flat pack note: all dimensions in inches (in parentheses in millimeters) 0.019 (0.48) 0.015 (0.38) 0.045 (1.14) max. pin 1 index 132 0.130 (3.30) 0.090 (2.29) 0.047 (1.19) 0.026 (0.66) 0.0065 (0.17) 0.004 (0.10) 0.370 (9.40) 0.300 (7.62) 0.828 (21.04) 0.812 (20.64) 0.055 (1.40) 0.045 (1.14) 0.440 (11.18) 0.430 (10.93) 0.347 (8.82) 0.333 (8.46) 0.005 (0.13) min.
20 x28c010 packaging information 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co C planarity 3926 fhd f13 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only 0.510" typical 0.050" typical 0.050" typical 0.300" ref footprint 0.400" 0.410" 0.030" typical 32 places
x28c010 21 packaging information 3926 fhd f21 36-lead ceramic pin grid array package type k 15 17 19 21 22 14 16 18 20 23 10 9 27 28 8 7 29 30 5 2 36 34 32 4 3 1 35 33 typ. 0.100 (2.54) all leads pin 1 index 0.050 (1.27) 0.008 (0.20) note: leads 5, 14, 23, & 32 12 11 25 26 13 6 31 24 a a typ. 0.180 (.010) (4.57 .25) 4 corners 0.770 (19.56) 0.750 (19.05) sq a a 0.185 (4.70) 0.175 (4.45) 0.020 (0.51) 0.016 (0.41) 0.072 (1.83) 0.062 (1.57) 0.120 (3.05) 0.100 (2.54) note: all dimensions in inches (in parentheses in millimeters) typ. 0.180 (.010) (4.57 .25) 4 corners
22 x28c010 packaging information 32-lead ceramic small outline gull wing package type r 3926 fhd f27 notes: 1. all dimensions in inches 2. formed lead shall be planar with respect to one another within 0.004 inches 0.340 0.007 see detail a for lead information 0.440 max. 0.560 nom. 0.0192 0.0138 0.050 0.750 0.005 0.840 max. 0.060 nom. 0.020 min. 0.015 r typ. 0.035 min. 0.015 r typ. 0.035 typ. 0.165 typ. detail a 0.560" typical 0.050" typical 0.050" typical footprint 0.030" typical 32 places
x28c010 23 packaging information 0.300 bsc 0.458 max. 0.450 0.008 pin 1 3926 fhd f35 0.035 x 45 ref. 0.085 0.010 0.020 (1.02) x 45 ref. typ. (3) plcs. 0.050 bsc 0.400 bsc 0.708 max. 0.060/0.120 pin #1 index corner note: 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: 1% nlt 0.005 (0.127) 0.700 0.010 0.005/0.015 0.025 0.003 0.050 0.005 0.006/0.022 detail a detail a 32-pad stretched ceramic leadless chip carrier package type n
24 x28c010 packaging information 3926 ill f39.2 note: 1. all dimensions are shown in millimeters (inches in parentheses). 0.50 0.04 (0.0197 0.0016) 0.30 0.05 (0.012 0.002) 14.80 0.05 (0.583 0.002) 1.30 0.05 (0.051 0.002) 0.17 (0.007) 0.03 (0.001) typical 40 places 15 eq. spc. @ 0.50 0.04 0.0197 0.016 = 9.50 0.06 (0.374 0.0024) overall tol. non-cumulative solder pads footprint 10.058 (0.396) 9.957 (0.392) 12.522 (0.493) 12.268 (0.483) pin #1 ident. o 1.016 (0.040) o 0.762 (0.030) 1 0.965 (0.038) 1.143 (0.045) 0.889 (0.035) 0.127 (0.005) dp. 0.076 (0.003) dp. x 0.065 (0.0025) 14.148 (0.557) 13.894 (0.547) seating plane a 0.178 (0.007) 1.016 (0.040) seating plane 15 typ. 0.500 (0.0197) 1.219 (0.048) 0.254 (0.010) 0.152 (0.006) 0.432 (0.017) 0.813 (0.032) typ. 0.432 (0.017) 0.508 (0.020) typ. 0.152 (0.006) typ. 4 typ. detail a 40-lead thin small outline package (tsop) type t
x28c010 25 ordering information device access time C12 = 120ns C15 = 150ns C20 = 200ns C25 = 250ns temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c mb = mil-std-883 package d = 32-lead cerdip e = 32-pad lcc f = 32-lead flat pack j = 32-lead plcc k = 36-lead pin grid array r = 32-lead hermetic soic (gull wing) n = 32-lead extended lcc t = 40-lead tsop x28c010 x x -x limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. xicor, inc. reserves the right to discontinue prod uction and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,88 3, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expe cted to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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